Aho, E., Vanne, J. &
Hämäläinen T. D. 2008. Configurable data memory for multimedia
processing. Journal of Signal Processing Systems 50, 2, pp. 231-249.
Aho, E., Vanne, J., Hämäläinen, T.D. &
Kuusilinna, K. 2005. Block-level parallel processing for scaling evenly
divisible frames. Proceedings of ISCAS 2005 IEEE International
Symposium on Circuits and Systems, 23-26 May 2005, Kobe, Japan pp.
1134-1137.
Aho, E., Vanne, J., Hämäläinen, T.D. &
Kuusilinna, K. 2005. Block-level parallel processing for scaling evenly
divisible images. IEEE Transactions on Circuits and Systems - I:
Regular Papers 52, 12, pp. 2717-2725.
Aho, E., Vanne, J., Hämäläinen, T.D. &
Kuusilinna, K. 2007. Configurable implementation of parallel memory
based real-time video downscaler. Microprocessors and Microsystems 31,
5, pp. 283-292.
Aho, E., Vanne, J. & Hämäläinen, T.D.
2006. Parallel memory architecture for arbitrary stride accesses.
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of
Electronic Circuits and Systems, 18-21 April, 2006, Prague, Czech
Republic pp. 65-70.
Aho, E., Vanne, J. & Hämäläinen, T.D.
2006. Parallel memory implementation for arbitrary stride accesses.
Proceedings of 2006 International Conference on Embedded Computer
Systems: Architectures, Modeling and Simulation, 17-20 July, 2006,
Samos, Greece pp. 1-6.
Aho, E., Vanne, J., Kuusilinna, K.,
Hämäläinen, T. & Saarinen, J. 2001. Configurable Address Computation
in a Parallel Memory Architecture. In: Antoniou, G. (ed.). Advances in
Signal Processing and Computer Technologies. Electrical and Computer
Engineering Series. A Series of Reference Books and Textbooks. Kreikka,
WSES Press. pp. 390-395.
Aho, E., Vanne, J., Kuusilinna, K.,
Hämäläinen, T. & Saarinen, J. 2001. Configurable Address Computation
in a Parallel Memory Architecture. Proceedings of the 5th WSES
International Conference on Circuits, Systems, Communications and
Computers (CSCC 2001), July 8-15, 2001, Rethymno, Greece pp. 4941-4946.
Aho, E., Vanne, J., Kuusilinna, K. &
Hämäläinen, T. 2002. Access Format Implementations in Configurable
Parallel Memory. Proceedings of ICIS 2002 the 2nd International
Conference on Computer and Information Science, August 8-9, 2002, Seoul,
Korea pp. 59-64.
Aho, E., Vanne, J., Kuusilinna, K. &
Hämäläinen, T.D. 2004. Address computation in configurable parallel
memory architecture. IEICE Transactions on Information and Systems
E87-D, 7, pp. 1674-1681.
Aho, E., Vanne, J., Kuusilinna, K. &
Hämäläinen, T.D. 2005. Comments on "Winscale: An image-scaling algorithm
using an area pixel model". IEEE Transactions on Circuits and Systems
for Video Technology 15, 3, pp. 454-455.
Aho, E., Vanne, J., Kuusilinna, K. &
Hämäläinen, T. 2002. Diamond Scheme Implementations in Configurable
Parallel Memory. Proceedings of IEEE Design and Diagnostics of
Electronic Circuits and Systems, April 17-19, 2002, Brno, Czech Republic
pp. 211-218.
Aho, E., Vanne, J., Kuusilinna, K. &
Hämäläinen, T. 2002. XOR-scheme Implementations In Configurable Parallel
Memory. In: Badawy, W. & Jullien G.A. (ed.). System-on-Chip for
Real-Time Applications. Kluwer Academic Publishers. pp. 249-261.
Aho, E., Vanne, J., Kuusilinna, K. &
Hämäläinen, T. 2002. Xor-scheme Implementations In Configurable Pararell
Memory. WSOC Proceedings of the International Workshop on System on
Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada pp.
287-298.
Haapala, K., Hämäläinen, T. &
Saarinen, J. 2001. Parallel Implementation of a Wavelet Based Still
Image Encoder. Proceedings of SCI 2001 (World Multiconference on
Systemics, Cybernetics and Informatics), July 22-25, 2001, Orlando,
Florida, USA 4, pp. 7-12.
Haapala, K., Kolinummi, P., Hämäläinen, T.
& Saarinen, J. 2000. Parallel DSP implementation of wavelet
transform in image compression. Proceedings of the IEEE International
Symposium on Circuits and Systems, ISCAS 2000, May 28-31, 2000, Geneva,
Switzerland 5, pp. 89-92.
Haapala, K., Kolinummi, P., Hämäläinen, T.
& Saarinen, J. 2000. Scalable DSP Realization of Wavelet Transform
in Image Coding. Proceedings, EUSIPCO 2000, September 4-8, 2000,
Tampere, Finland 1, pp. 247-250.
Haapala, K., Lappalainen, V. &
Hämäläinen, T.D. 2005. Experimental parallel implementation of a
wavelet-based still image encoder. Microprocessors and Microsystems 29,
4, pp. 155-167.
Hallapuro, A., Lappalainen, V. &
Hämäläinen, T.D. 2001. Performance analysis of low bit rate H.26L video
encoder. Proceedings of ICASSP 2001 Conference, May 7-11, 2001, Salt
Lake City, Utah, USA Volume II, DISPS-L-3.5, pp. 4 s.
Kolinummi, P., Särkijärvi, J., Hämäläinen,
T. & Saarinen, J. 2000. H.263 Video Encoder Implementation on a
Scalable System. Proceedings, EUSIPCO 2000, September 4-8, 2000,
Tampere, Finland 3, pp. 1721-1724.
Kolinummi, P., Särkijärvi, J., Hämäläinen,
T. & Saarinen, J. 2000. Scalable implementation of H.263 Video
encoder on a parallel DSP system. ISCAS 2000, Proceedings of the IEEE
International Symposium on Circuits and Systems, May 28-31, 2000,
Geneva, Switzerland 1, pp. 551-554.
Kukkala, P., Setälä, M., Arpinen, T.,
Salminen, E., Hännikäinen, M. & Hämäläinen, T.D. 2007. Implementing a
WLAN Video Terminal Using UML and Fully Automated Design Flow. EURASIP
Journal on Embedded Systems, Embedded Digital Signal Processing Systems
2007, 85029, pp. 15 p.
Kulmala, A., Hämäläinen, T.D. &
Hännikäinen, M. 2006. Comparison of GALS and synchronous architectures
with MPEG-4 video encoder on multiprocessor system-on-chip FPGA.
Proceedings of 9th Euromicro Conference on Digital System Design
Architectures, Methods and Tools, 30 August-1 September, 2006,
Dubrovnik, Croatia pp. 83-86.
Kulmala, A., Hämäläinen, T.D. &
Hännikäinen, M. 2006. Reliable GALS implementations of MPEG-4 encoder
with mixed clock FIFO on standard FPGA. Proceedings of 2006
International Conference on Field Programmable Logic and Applications,
28-30 August, 2006, Madrid, Spain pp. 495-500.
Kulmala, A., Lehtoranta, O., Hämäläinen,
T.D. & Hännikäinen, M. 2006. Scalable MPEG-4 encoder on FPGA
multiprocessor SOC. Eurasip journal on embedded systems 2006, 38494, pp.
1-15.
Kulmala, A., Salminen, E. & Hämäläinen
T.D. 2008. Distributed bus arbitration algorithm comparison on
FPGA-based MPEG-4 multiprocessor system on chip. IET Computers &
Digital Techniques 2, 4, pp. 314-325.
Kulmala, A., Salminen, E. &
Hämäläinen, T.D. 2006. Distributed bus arbitration algorithm comparison
on FPGA based MPEG-4 multiprocessor SoC. Proceedings of 24th Norchip
Conference, 20-21 November, 2006, Linköping, Sweden pp. 167-170.
Kulmala, A., Salminen, E. &
Hämäläinen, T.D. 2007. Instruction memory architecture evaluation on
multiprocessor FPGA MPEG-4 encoder. Proceedings of 2007 IEEE Design and
Diagnostics of Electronic Circuits and Systems, 11-13 April, 2007,
Kraków, Poland 07EX1759, pp. 105-110.
Kulmala, A., Salminen, E., Hännikäinen, M.
& Hämäläinen, T.D. 2006. Evaluating SoC network performance in
MPEG-4 encoder. The 2006 IEEE Workshop on Signal Processing Systems,
Design and Implementation., 2-4 October, 2006, Banff, Canada pp.
271-276.
Kulmala, A., Salminen, E., Lehtoranta, O.,
Hämäläinen, T.D. & Hännikäinen, M. 2006. Impact of shared
instruction memory on performance of FPGA-based MP-SoC video encoder.
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of
Electronic Circuits and Systems, 18-21, 2006, Prague, Czech Republic pp.
59-64.
Lahti, J., Juntunen, J.K., Lehtoranta, O.
& Hämäläinen, T.D. 2005. Algorithmic optimization of H.264/AVC
encoder. Proceedings of ISCAS 2005 IEEE International Symposium on
Circuits and Systems, 23-26 May 2005, Kobe, Japan pp. 3463-3466.
Lappalainen, V., Hallapuro, A. &
Hämäläinen, T.D. 2003. Complexity of Optimized H.26L Video Decoder
Implementation. IEEE Transactions on Circuits and Systems for Video
Technology 13, 7, pp. 717-725.
Lappalainen, V., Hallapuro, A. &
Hämäläinen, T.D. 2001. Optimized Implementations of Emerging H.26L Video
Decoder on Pentium III. In: Antoniou, G. (ed.). Advances in Signal
Processing and Computer Technologies. Electrical and Computer
Engineering Series. A Series of Reference Books and Textbooks. Kreikka,
WSES Press. pp. 233-238.
Lappalainen, V., Hallapuro, A. &
Hämäläinen, T.D. 2001. Optimized Implementations of Emerging H.26L Video
Decoder on Pentium III. Proceedings of the 5th WSES International
Conference on Circuits, Systems, Communications and Computers (CSCC
2001), July 8-15, 2001, Rethymno, Greece pp. 3981-3986.
Lappalainen, V., Hallapuro, A. &
Hämäläinen, T.D. 2003. Performance of H.26L Video Encoder on
General-Purpose Processor. Journal of VLSI signal processing systems for
signal, image, and video technology 34, 3, pp. 239-249.
Lappalainen, V., Hallapuro, A. &
Hämäläinen, T.D. 2001. Performance of H.26L Video Encoder on
General-Purpose Processor. Proceedings of ICCE 2001, International
Conference on Consumer Electronics, June 19-21, 2001, Los Angeles,
California, USA pp. 266-267.
Lappalainen, V., Hallapuro, A. &
Hämäläinen, T. 2001. Optimization of Emerging H.26L Video Encoder.
Proceedings of the 2001 IEEE Workshop on Signal Processing Systems SIPS
2001, September 26-28, 2001, Antwerp, Belgium pp. 406-415.
Lappalainen, V., Hämäläinen, T.D. &
Hallapuro, A. 2001. Optimization of H.26L Video Decoder. Proceedings of
VIPromCom-2001, 3rd International Symposium on Video Processing and
Multimedia Communications, June 13-15, 2001, Zadar, Croatia pp. 91-93.
Lappalainen, V. & Hämäläinen, T. 2001.
Overview of Research Efforts on Video Coding with Media ISA Extensions.
Proceedings of SCI 2001 (World Multiconference on Systemics,
Cybernetics and Informatics), July 22-25, 2001, Orlando, Florida, USA 4,
pp. 19-24.
Lappalainen, V. & Hämäläinen, T. 2002.
Unified Method for Optimization of Several Video Coding Algorithms on
General-Purpose Processors. Proceedings of the International Conference
on Information Technology: Coding and Computing ITCC 2002, April 8-10,
2002, Las Vegas, Nevada, USA pp. 431-438.
Lappalainen, v., Hämäläinen, T. &
Liuha, P. 2002. Overview of Research Efforts on Media ISA Extensions and
Their Usage in Video Coding. IEEE Transactions on Circuits and Systems
for Video Technology 12, 8, pp. 660-670.
Lehtoranta, O., Hämäläinen, T.,
Lappalainen, V. & Mustonen, J. 2002. Parallel implementation of
video encoder on quad DSP system. Microprocessors and Microsystems 26,
pp. 1-15.
Lehtoranta, O., Hämäläinen, T. &
Lappalainen, V. 2002. Detecting Corrupted Intra Macroblocks in H.263.
Proceedings of the 2002 IEEE Fifth Workshop on Multimedia Signal
Processing, December 9-11, 2002, St.Thomas, US Virgin Islands, USA pp. 4
s.
Lehtoranta, O., Hämäläinen, T. &
Saarinen, J. 2000. Real-time H.263 Encoding of QCIF-images on
TMS320C6201 Fixed Point DSP. Proceedings of the IEEE International
Symposium on Circuits and Systems, ISCAS 2000, May 28-31, 2000, Geneva,
Switzerland 1, pp. 583-586.
Lehtoranta, O., Hämäläinen, T. &
Saarinen, J. 2000. Real-time implementation of H.263 video encoder on
TMS320C6201 Fixed Point DSP. Proceedings, EUSIPCO 2000, September 4-8,
2000, Tampere, Finland 3, pp. 1457-1460.
Lehtoranta, O. & Hämäläinen, T.D.
2003. Complexity Analysis of Spatially Scalable MPEG-4 Encoder.
Proceedings of the 2003 International Symposium on System-on-Chip,
November 19-21, 2003, Tampere, Finland pp. 57-60.
Lehtoranta, O. & Hämäläinen, T.D.
2005. Feasibility study of a real-time operating system for a
multi-channel MPEG-4 encoder. Proceedings of the Conference Multimedia
on Mobile Devices, 17-18 January 2005, San Jose, USA.SPIE Proceedings
5684, pp. 293-299.
Lehtoranta, O., Hännikäinen, M., Suhonen,
J. & Hämäläinen T.D. 2002. Implementation of Unequal Error
Protection of H.263 Video for a Wireless Video Demonstrator. Proceeding
of the International Conference of Telecommunications 2002, June 23-26,
2002, Beijing, China 1, pp. 1024-1029.
Lehtoranta, O., Kukkala, P., Hämäläinen,
T.D. & Lappalainen, V. 2003. Implementation of a Video Transcoder
for Embedded System. In: Srimani, P.K.et al.International Conference on
Information Technology: Coding and Computing, ITCC 2003 pp. 389-395.
Lehtoranta, O., Salminen, E., Kulmala, A.,
Hännikäinen, M. & Hämäläinen, T.D. 2005. A parallel MPEG-4 encoder
for FPGA based multiprocessor SoC. Proceedings of 2005 International
Conference on Field Programmable Logic and Applications (FPL 2005),
24-26 August 2005, Tampere, Finland pp. 380-385.
Lehtoranta, O., Suhonen, J., Hännikäinen,
M., Lappalainen, V. & Hämäläinen T.D. 2003. Comparison of video
protection methods for wireless networks. Signal Processing: Image
Communication 18, pp. 861-877.
Määttä, J., Vanne, J., Hämäläinen, T.D.
& Nikkanen, J. 2011. Generic Software Framework for a
Line-Buffer-Based Image Processing Pipeline. IEEE Transactions on
Consumer Electronics 57, 3, pp. 1442-1449.
Rasmus, A., Kulmala, A., Salminen, E.
& Hämäläinen, T.D. 2007. IP integration overhead analysis in
system-on-chip video encoder. Proceedings of 2007 IEEE Design and
Diagnostics of Electronic Circuits and Systems, 11-13 April, 2007,
Kraków, Poland 07EX1759, pp. 333-336.
Salminen, E., Hämäläinen, T., Kangas, T.,
Kuusilinna, K. & Saarinen, J. 2001. Interfacing multiple processors
in a system-on-chip video encoder. Proceedings of ISCAS 2001 Conference,
May 6-9, 2001, Sydney, Australia pp. 478-481.
Salminen, E., Kangas, T. & Hämäläinen,
T.D. 2006. The impact of communication on the scalability of the
data-parallel video encoder on MPSoC. Proceedings of 2006 International
Symposium on System-on-Chip, 13-16 November, 2006, Tampere, Finland pp.
191-194.
Vanne, J., Aho, E., Hämäläinen, T.D. &
Kuusilinna, K. 2006. A high-performance sum of absolute difference
implementation for motion estimation. IEEE Transactions on Circuits and
Systems for Video Technology 16, 7, pp. 876-883.
Vanne, J., Aho, E. & Hämäläinen, T.D.
2008. Menetelmä ja rinnakkaismuistijärjestelmä
liikkeenestimointialgoritmeille. Pat.FI 119167 B pp. 44 + liitt.
Vanne, J., Aho, E. & Hämäläinen, T.D.
2007. Piiri ja menetelmä erojen itseisarvojen summan laskemiseksi
nopeasti ja tehokkaasti.Krets och metod för att räkna en sum av absoluta
skillnader snabbt och effektivt. Pat.FI 117956 B pp. 35 s + liitt.
Vanne, J., Aho, E., Hämäläinen, T.D. &
Kuusilinna, K. 2008. A parallel memory system for variable block-size
motion estimation algorithms. IEEE Transactions on Circuits and Systems
for Video Technology 18, 4, pp. 538-543.
Vanne, J., Aho, E., Kuusilinna, K. &
Hämäläinen, T. 2002. Configurable Paralell Memory Implementation For
Systenm-on-Chip Designs. WSOC Proceedings of the International Workshop
on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff,
Canada pp. 253-264.
Vanne, J., Aho, E., Kuusilinna, K. &
Hämäläinen, T. 2002. Configurable Parallel Memory Implementation For
System-on-Chip Designs. In: Badawy, W. & Jullien G.A. (ed.).
System-on-Chip for Real-Time Applications. Kluwer Academic Publishers.
pp. 237-248.
Vanne, J., Aho, E., Kuusilinna, K. &
Hämäläinen, T. 2002. Co-simulation of Configurable Parallel Memory
Architecture and Processor. Proceedings of IEEE Design and Diagnostics
of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno,
Czech Republic pp. 310-313.
Vanne, J., Aho, E., Kuusilinna, K. &
Hämäläinen, T.D. 2009. A configurable motion estimation architecture for
block-matching algorithms. IEEE Transactions on Circuits and Systems
for Video Technology 19, 4, pp. 466-476.
Vanne, J., Aho, E., Kuusilinna, K. &
Hämäläinen, T. 2002. Enhanced Configurable Parallel Memory Architecture.
Proceedings of DCD 2002 Euromicro Symposium on Digital System Design;
Architectures, Methods and Tools, September 4-6, 2002, Dortmund, Germany
pp. 28-35.
Viitanen, M., Vanne, J., Hämäläinen, T.D.,
Lainema, J. & Ugur, K. 2011. HM 4.0 entropy coding complexity
considerations. Joint Collaborative Team on Video Coding (JCT-VC) of
ITU-T-SG16 WP3 and ISO/IEC JTC1/SC29/WG11, 7th Meeting Geneva, CH, 21-30
November, 2011 pp. 1-4.
Viitanen, M. & Hämäläinen, T.D. 2004.
Comparison of data dependence analysis tests. Lecture notes in computer
science 3133, pp. 149-158.
Viitanen, M., Kolinummi, P., Hämäläinen,
T. & Saarinen J. 2000. Scalable DSP Implementation of DCT-based
Motion Estimation Algorithm. Proceedings, Signal Processing X, Theories
and Applications, Volume I, EUSIPCO 2000, September 4-8, 2000, Tampere,
Finland 1, pp. 251-254.
