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uvgKvazaarHW
uvgKvazaarHW is an academic open-source hardware video encoder for High Efficiency Video Coding (HEVC/H.265), developed from the Kvazaar open-source software encoder. uvgKvazaarHW is being developed under the BSD-3-Clause license
The current version of uvgKvazaarHW supports all normative HEVC intra coding tools with proven real-time encoding speed up to 4K resolution on an Arria10 PCIe FPGA. It is implemented using High-level Synthesis (HLS) and an HLS-tool called Catapult. The open-source Kactus2 IP-XACT tool has been used to create component descriptions that follow the IP-XACT standard for better modularity, reusability, and downstream integration. uvgKvazaarHW includes HLS synthesis-ready source codes and a SystemC simulation framework using Verilator for validation and development.
Please cite the following paper for any usage of uvgKvazaarHW:
P. Sjövall, A. Lemmetti, J. Vanne, S. Lahti, and T. D. Hämäläinen, “High-level synthesis implementation of an embedded real-time HEVC intra encoder on FPGA for media applications, ” ACM Trans. Des. Autom. Electron. Syst., vol. 27, no. 4, pp. 1-34, Mar. 2022. [Tuni.fi] [PDF]
Publications
Journals:
P. Sjövall, A. Lemmetti, J. Vanne, S. Lahti, and T. D. Hämäläinen, “High-level synthesis implementation of an embedded real-time HEVC intra encoder on FPGA for media applications,” ACM Trans. Des. Autom. Electron. Syst., vol. 27, no. 4, pp. 1-34, Mar. 2022. [Tuni.fi] [PDF]
S. Lahti, P. Sjövall, J. Vanne, and T. D. Hämäläinen, “Are we there yet? A study on the state of high-level synthesis,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 38, no. 5, pp. 898-911, May 2018. [Tuni.fi] [PDF]
Conferences:
P. Sjövall, A. Mercat, and J. Vanne, “FPGA-accelerated HEVC encoder for energy-efficient multi-access edge computing,” in Proc. IEEE Int. Conf. Image Processing, Kuala Lumpur, Malaysia, Oct. 2023. [Tuni.fi] [PDF]
P. Sjövall, M. Rasinen, A. Lemmetti, and J. Vanne, “High-level synthesis implementation of an accurate HEVC interpolation filter on an FPGA,” in Proc. IEEE Nordic Circuits Syst. Conf., Oslo, Norway, Oct. 2021. [Tuni.fi] [PDF]
T. Partanen, P. Sjövall, A. Lemmetti, and J. Vanne, “High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding,” in Proc. IEEE Int. Symp. Circuits Syst., Daegu, Korea, May 2021. [Tuni.fi] [PDF]
P. Sjövall, M. Teuho, A. Oinonen, J. Vanne, and T. D. Hämäläinen, “Visualization of dynamic resource allocation for HEVC encoding in FPGA-accelerated SDN cloud,” in Proc. IEEE Visual Comm. and Image Proc., Sydney, Australia, Dec. 2019. [Tuni.fi] [PDF]
P. Sjövall, A. Oinonen, M. Teuho, J. Vanne, and T. D. Hämäläinen, “Dynamic resource allocation for HEVC encoding in FPGA-accelerated SDN cloud,” in Proc. IEEE Nordic Circuits Syst. Conf., Helsinki, Finland, Oct. 2019. [Tuni.fi] [PDF]
P. Sjövall, V. Viitamäki, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “FPGA-powered 4K120p HEVC intra encoder,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018. [Tuni.fi] [PDF]
V. Viitamäki, P. Sjövall, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “Live demonstration: 4K100p HEVC intra encoder,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018. [Tuni.fi] [PDF]
P. Sjövall, V. Viitamäki, A. Oinonen, J. Vanne, T. D. Hämäläinen, and A. Kulmala “Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server,” in Proc. IEEE Workshop Signal Process. Syst., Lorient, France, Oct. 2017. [Tuni.fi] [PDF]
V. Viitamäki, P. Sjövall, J. Vanne, and T. D. Hämäläinen, “High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA,” in Proc. IEEE Int. Symp. Circuits Syst., Baltimore, Maryland, USA, May 2017. [Tuni.fi] [PDF]
P. Sjövall, V. Viitamäki, J. Vanne, and T. D. Hämäläinen, “High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA,” in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Process., New Orleans, Louisiana, USA, Mar. 2017. [Tuni.fi] [PDF]
P. Sjövall, J. Virtanen, J. Vanne, and T. D. Hämäläinen, “High-level synthesis design flow for HEVC intra encoder on SoC-FPGA,” in Proc. Euromicro Symp. Digit. Syst. Des., Funchal, Madeira, Portugal, Aug. 2015, pp. 49-56. [Tuni.fi]