Page content last modified on 2024-02-14.

Most relevant journal articles

2023:

A. Tissier, W. Hamidouche, S. B. D. Mdalsi, J. Vanne, F. Galpin, and D. Menard, “Machine Learning Based Efficient QT-MTT Partitioning Scheme for VVC Intra Encoders,” IEEE Trans. Circuits Syst. Video Technol., vol. 33, no. 8, pp. 4279-4293, Jan. 2023. [Tuni.fi]

2022:

J. Sainio, A. Mercat, and J. Vanne, “Design space exploration of practical VVC encoding for emerging media applications,” IEEE Trans. Consumer Electron., vol. 68, no. 4, pp. 387-400, Nov. 2022. [Tuni.fi] [PDF]

P. Sjövall, A. Lemmetti, J. Vanne, S. Lahti, and T. D. Hämäläinen, “High-level synthesis implementation of an embedded real-time HEVC intra encoder on FPGA for media applications,” ACM Trans. Des. Autom. Electron. Syst., vol. 27, no. 4, pp. 1-34, Mar. 2022. [Tuni.fi] [PDF]

M. Viitanen, J. Sainio, A. Mercat, A. Lemmetti, and J. Vanne, “From HEVC to VVC: the first development steps of a practical intra video encoder,” IEEE Trans. Consumer Electron., vol. 68, no. 2, pp. 139-148, Jan. 2022. [Tuni.fi] [PDF]

J. Žádník, M. Mäkitalo, J. Vanne, and P. Jääskeläinen, “Image and video coding techniques for ultra-low latency,” ACM Comput. Surv., vol. 54, no. 11, Article 231, pp. 1-35, Jan. 2022. [Tuni.fi] [PDF]

2021:

A. Mercat, A. Mäkinen, J. Sainio, A. Lemmetti, M. Viitanen, and J. Vanne, “Comparative rate-distortion-complexity analysis of VVC and HEVC video codecs,” IEEE Access, vol. 9, pp. 67813-67828, May 2021. [Tuni.fi] [PDF]

2018 and before:

S. Lahti, P. Sjövall, J. Vanne, and T. D. Hämäläinen, “Are we there yet? A study on the state of high-level synthesis,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 38, no. 5, pp. 898-911, May 2018.[Tuni.fi] [PDF]

J. Vanne, M. Viitanen, and T. D. Hämäläinen, “Efficient mode decision schemes for HEVC inter prediction,” IEEE Trans. Circuits Syst. Video Technol., vol. 24, no. 9, pp. 1579-1593, Sept. 2014.[Tuni.fi] [PDF]

J. Vanne, M. Viitanen, T. D. Hämäläinen, and A. Hallapuro, “Comparative rate-distortion-complexity analysis of HEVC and AVC video codecs,” IEEE Trans. Circuits Syst. Video Technol., vol. 22, no. 12, pp. 1885-1898, Dec. 2012.[Tuni.fi] [PDF]

J. M. Määttä, J. Vanne, T. D. Hämäläinen, and J. Nikkanen, “Generic software framework for a line-buffer-based image processing pipeline,” IEEE Trans. Consumer Electron., vol. 57, no. 3, pp. 1442-1449, Aug. 2011.[Tuni.fi]

J. Vanne, E. Aho, K. Kuusilinna, and T. D. Hämäläinen, “A configurable motion estimation architecture for block-matching algorithms,” IEEE Trans. Circuits Syst. Video Technol., vol. 19, no. 4, pp. 466-476, Apr. 2009.[Tuni.fi]

J. Vanne, E. Aho, T. D. Hämäläinen, and K. Kuusilinna, “A parallel memory system for variable block-size motion estimation algorithms,” IEEE Trans. Circuits Syst. Video Technol., vol. 18, no. 4, pp. 538-543, Apr. 2008.[Tuni.fi]

J. Vanne, E. Aho, T. D. Hämäläinen, and K. Kuusilinna, “A high-performance sum of absolute difference implementation for motion estimation,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 7, pp. 876-883, July 2006.[Tuni.fi]

E. Aho, J. Vanne, T. D. Hämäläinen, and K. Kuusilinna, “Block-level parallel processing for scaling evenly divisible images,” IEEE Trans. Circuits Syst. I, vol. 52, no. 12, pp. 2717-2725, Dec. 2005.[Tuni.fi]

E. Aho, J. Vanne, K. Kuusilinna, and T. D. Hämäläinen, “Comments on "Winscale: an image-scaling algorithm using an area pixel model",” IEEE Trans. Circuits Syst. Video Technol., vol. 15, no. 3, pp. 454-455, Mar. 2005.[Tuni.fi]

V. Lappalainen, A. Hallapuro, and T. D. Hämäläinen, “Complexity of optimized H.26L video decoder implementation,” IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, pp. 717-725, July 2003.[Tuni.fi]

V. Lappalainen, T. D. Hämäläinen, and P. Liuha, “Overview of research efforts on media ISA extensions and their usage in video coding,” IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 8, pp. 660-670, Aug. 2002.[Tuni.fi]

Most relevant conference articles

2023:

J. Sainio, A. Mercat, and J. Vanne, “Vectorized and optimized dependent quantization for practical VVC encoding,” in Proc. IEEE Visual Comm. Image Proc., Jeju, Korea, Dec. 2023. [Tuni.fi] [PDF]

K. Siivonen, J. Sainio, A. Mercat, and J. Vanne, “Tailored AVX2 transform kernels for Versatile Video Coding,” in Proc. IEEE Nordic Circuits Syst. Conf., Aalborg, Denmark, Oct.-Nov. 2023. [Tuni.fi] [PDF]

E. Gałązka, A. Leppäaho, and J. Vanne, “CiThruS2: open-source virtual environment for simulating real-time drone operations and piloting,” in Proc. IEEE Int. Automated Vehicle Validation Conf., Austin, Texas, USA, Oct. 2023. [Tuni.fi] [PDF]

P. Sjövall, A. Mercat, and J. Vanne, “FPGA-accelerated HEVC encoder for energy-efficient multi-access edge computing,” in Proc. IEEE Int. Conf. Image Processing, Kuala Lumpur, Malaysia, Oct. 2023. [Tuni.fi] [PDF]

G. Gautier, A. Mercat, L. Fréneau, M. Pitkänen, and J. Vanne, “UVG-VPC: voxelized point cloud dataset for visual volumetric video-based coding,” in Proc. Int. Conf. Qual. Multimedia Exper., Ghent, Belgium, June 2023. [Tuni.fi] [PDF]

M. Viitanen, J. Sainio, A. Mercat, G. Gautier, J. Vanne, I. Farhat, P.-L. Cabarat, W. Hamidouche, and D. Menard, “Open-source toolkit for live end-to-end 4K VVC intra coding,” in Proc. ACM Multimedia Syst. Conf., Vancouver, Canada, June 2023. [Tuni.fi] [PDF]

J. Sainio, A. Mercat, and J. Vanne, “RDO candidate selection for maximizing coding efficiency in a practical HEVC encoder,” in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Process., Rhodes Island, Greece, June 2023. [Tuni.fi] [PDF]

A. Mercat, A. Lemmetti, J. Sainio, and J. Vanne, “AVX2-Optimized interpolation filters for HEVC inter encoding,” in Proc. IEEE Int. Symp. Circuits and Syst., Monterey, California, USA, May 2023. [Tuni.fi] [PDF]

2022:

A. Mercat, S. Ahovainio, and J. Vanne, “Spatio-temporal parallelization scheme for HEVC encoding on multi-computer systems,” in Proc. IEEE Int. Conf. Image Processing, Bordeaux, France, Oct. 2022. [Tuni.fi] [PDF]

A. Tissier, W. Hamidouche, J. Vanne, and D. Menard, “Machine learning based efficient QT-MTT partitioning for VVC inter coding,” in Proc. IEEE Int. Conf. Image Processing, Bordeaux, France, Oct. 2022. [Tuni.fi] [PDF]

J. Laitinen, A. Mercat, J. Vanne, H. Rezazadegan Tavakoli, F. Cricri, E. Aksu, and M. Hannuksela, “Efficient topology coding and payload partitioning techniques for neural network compression (NNC) standard,” in Proc. IEEE Int. Conf. Multimedia Expo Workshops, Taipei City, Taiwan, July 2022. [Tuni.fi] [PDF]

2021:

J. Räsänen, A. Altonen, A. Mercat, and J. Vanne, “Open-source RTP library for end-to-end encrypted real-time video streaming applications,” in Proc. IEEE Int. Symp. Multimedia, Naples, Italy, Nov.-Dec. 2021. [Tuni.fi] [PDF]

P. Sjövall, M. Rasinen, A. Lemmetti, and J. Vanne, “High-level synthesis implementation of an accurate HEVC interpolation filter on an FPGA,” in Proc. IEEE Nordic Circuits Syst. Conf., Oslo, Norway, Oct. 2021. [Tuni.fi] [PDF]

J. Sainio, A. Mercat, and J. Vanne, “uvgVenctester: open-source test automation framework for comprehensive video encoder benchmarking,” in Proc. ACM Multimedia Syst. Conf., Istanbul, Turkey, Sept.-Oct. 2021. [Tuni.fi] [PDF]

T. T. Niemirepo, M. Viitanen, and J. Vanne, “Open3DGen: Open-Source software for reconstructing textured 3D models from RGB-D images,” in Proc. ACM Multimedia Syst. Conf., Istanbul, Turkey, Sept.-Oct. 2021. [Tuni.fi] [PDF]

E. Gałązka, T. T. Niemirepo, and J. Vanne, “CiThruS2: open-source photorealistic 3D framework for driving and traffic simulation in real time,” in Proc. IEEE Int. Conf. Intell. Transp. Syst., Indianapolis, Indiana, USA, Sept. 2021. [Tuni.fi] [PDF]

A. Altonen, J. Räsänen, A. Mercat, and J. Vanne, “uvgRTP 2.0: open-source RTP library for real-time VVC/HEVC streaming,” in Proc. IEEE Int. Conf. Multimedia Expo, Shenzhen, China, July 2021. [Tuni.fi] [PDF]

T. Partanen, P. Sjövall, A. Lemmetti, and J. Vanne, “High-level synthesis implementation of transform-exempted SATD architectures for low-power video coding,” in Proc. IEEE Int. Symp. Circuits Syst., Daegu, Korea, May 2021. [Tuni.fi] [PDF]

J. Sainio, A. Mercat, and J. Vanne, “Parallel implementations of lambda domain and R-lambda model rate control schemes in a practical HEVC encoder,” in Proc. Data Compression Conf., Snowbird, Utah, USA, Mar. 2021. [Tuni.fi] [PDF]

2020:

J. Räsänen, A. Altonen, A. Mercat, and J. Vanne, “Live demonstration: interactive quality of experience evaluation in Kvazzup video call,” in Proc. IEEE Int. Symp. Multimedia, Naples, Italy, Dec. 2020. [Tuni.fi] [PDF]

T. T. Niemirepo, M. Viitanen, and J. Vanne, “Binocular multi-CNN system for real-time 3D pose estimation,” in Proc. ACM Int. Conf. Multimedia, Seattle, Washington, USA, Oct. 2020. [Tuni.fi] [PDF]

J. Laitinen, A. Lemmetti, and J. Vanne, “Real-time implementation of scalable HEVC encoder,” in Proc. IEEE Int. Conf. Image Processing, Abu Dhabi, United Arab Emirates, Oct. 2020. [Tuni.fi] [PDF]

A. Tissier, W. Hamidouche, J. Vanne, F. Galpin, and D. Menard, “CNN oriented complexity reduction of VVC intra encoder,” in Proc. IEEE Int. Conf. Image Processing, Abu Dhabi, United Arab Emirates, Oct. 2020. [Tuni.fi] [PDF]

A. Altonen, J. Räsänen, J. Laitinen, M. Viitanen, and J. Vanne, “Open-source RTP library for high-speed 4K HEVC video streaming,” in Proc. IEEE Int. Workshop on Multimedia Signal Processing, Tampere, Finland, Sept. 2020. [Tuni.fi] [PDF]

A. Lemmetti, M. Viitanen, A. Mercat, and J. Vanne, “Kvazaar 2.0: fast and efficient open-source HEVC inter encoder,” in Proc. ACM Multimedia Syst. Conf., Istanbul, Turkey, June 2020. [Tuni.fi] [PDF]

A. Mercat, M. Viitanen, and J. Vanne, “UVG dataset: 50/120fps 4K sequences for video codec analysis and development,” in Proc. ACM Multimedia Syst. Conf., Istanbul, Turkey, June 2020. [Tuni.fi] [PDF]

S. Ahovainio, A. Mercat, and J. Vanne, “Live demonstration: multi-laptop HEVC encoding,” in Proc. IEEE Int. Symp. Circuits Syst., Seville, Spain, May 2020. [Tuni.fi] [PDF]

S. Ahovainio, A. Mercat, M. Viitanen, and J. Vanne, “Multi-Level parallelization scheme for distributed HEVC encoding on multi-computer systems,” in Proc. IEEE Int. Symp. Circuits Syst., Seville, Spain, May 2020. [Tuni.fi] [PDF]

2019:

T. Niemirepo, J. Toivonen, M. Pitkänen, M. Viitanen, and J. Vanne, “Demo: CiThruS traffic scene simulator,” in Proc. IEEE Vehicular Networking Conf., Los Angeles, California, USA, Dec. 2019. [Tuni.fi] [PDF]

P. Sjövall, M. Teuho, A. Oinonen, J. Vanne, and T. D. Hämäläinen, “Visualization of dynamic resource allocation for HEVC encoding in FPGA-accelerated SDN cloud,” in Proc. IEEE Visual Comm. and Image Proc., Sydney, Australia, Dec. 2019. [Tuni.fi] [PDF]

M. Atokari, M. Viitanen, A. Mercat, E. Kattainen, and J. Vanne, “Parallax-tolerant 360 live video stitcher,” in Proc. IEEE Int. Conf. Visual Comm. and Image Proc., Sydney, Australia, Dec. 2019. [Tuni.fi] [PDF]

T. Niemirepo, J. Toivonen, M. Viitanen, and J. Vanne, “Open-source CiThruS simulation environment for real-time 360-degree traffic imaging,” in Proc. IEEE Int. Conf. Connected Vehicles and Expo, Graz, Austria, Nov. 2019. [Tuni.fi] [PDF]

P. Sjövall, A. Oinonen, M. Teuho, J. Vanne, and T. D. Hämäläinen, “Dynamic resource allocation for HEVC encoding in FPGA-accelerated SDN cloud,” in Proc. IEEE Nordic Circuits Syst. Conf., Helsinki, Finland, Oct. 2019. [Tuni.fi] [PDF]

M. Pitkänen, M. Viitanen, A. Mercat, and J. Vanne, “Remote VR gaming on mobile devices,” in Proc. ACM Int. Conf. Multimedia, Nice, France, Oct. 2019. [Tuni.fi] [PDF]

A. Tissier, A. Mercat, T. Amestoy, W. Hamidouche, J. Vanne, and D. Menard, “Complexity reduction opportunities in the future VVC intra encoder,” in Proc. IEEE Int. Workshop on Multimedia Signal Processing, Kuala Lumpur, Malaysia, Sept. 2019. [Tuni.fi] [PDF]

A. Mercat, A. Lemmetti, M. Viitanen, and J. Vanne, “Acceleration of Kvazaar HEVC intra encoder with machine learning,” in Proc. IEEE Int. Conf. Image Processing, Taipei, Taiwan, Sept. 2019. [Tuni.fi] [PDF]

J. Sainio, A. Mercat, and J. Vanne, “Hardware deceleration of Kvazaar HEVC encoder,” in Proc. Int. Conf. Embedded Comput. Syst.: Architectures, Model. Simul., Samos, Greece, July 2019. [Tuni.fi] [PDF]

A. Altonen, M. Viitanen, J. Räsänen, A. Mercat, and J. Vanne, “Public and open HEVC encoding service in the cloud,” in Proc. ACM Multimedia Syst. Conf., Amherst, Massachusetts, USA, June 2019. [Tuni.fi] [PDF]

2018:

K. Siivonen, J. Sainio, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Open framework for error-compensated gaze data collection with eye tracking glasses,” in Proc. IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2018. [Tuni.fi] [PDF]

J. Räsänen, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Live demonstration: Kvazzup 4K HEVC video call,” in Proc. IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2018. [Tuni.fi] [PDF]

J. Sainio, A. Ylä-Outinen, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Eye-controlled region of interest HEVC encoding,” in Proc. IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2018. [Tuni.fi] [PDF]

M. Abutaha, N. Sidaty, W. Hamidouche, J. Vanne, O. Déforges, and S. El Assad, “End-to-end real-time ROI-based encryption in HEVC videos,” in Proc. Eur. Signal Process. Conf., Rome, Italy, Sept. 2018. [Tuni.fi]

M. Viitanen, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “Low latency edge rendering scheme for interactive 360 degree virtual reality gaming,” in Proc. IEEE Int. Conf. Distrib. Comput. Syst., Vienna, Austria, July 2018. [Tuni.fi] [PDF]

A. Heikkinen, P. Pääkkönen, M. Viitanen, J. Vanne, T. Riikonen, and K. Bakanoglu, “Fast and easy live video service setup using lightweight virtualization,” in Proc. ACM Multimedia Syst. Conf., Amsterdam, The Netherlands, June 2018. [Tuni.fi] [PDF]

P. Sjövall, V. Viitamäki, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “FPGA-powered 4K120p HEVC intra encoder,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018. [Tuni.fi] [PDF]

V. Viitamäki, P. Sjövall, J. Vanne, T. D. Hämäläinen, and A. Kulmala, “Live demonstration: 4K100p HEVC intra encoder,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018. [Tuni.fi] [PDF]

N. Sidaty, M. Viitanen, W. Hamidouche, J. Vanne, and O. Déforges, “Live demonstration: end-to-end real-time ROI-based encryption in HEVC videos,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018. [Tuni.fi] [PDF]

A. Lemmetti, E. Kallio, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Rate-distortion-complexity optimized coding scheme for Kvazaar HEVC intra encoder,” in Proc. Data Compression Conf., Snowbird, Utah, USA, Mar. 2018. [Tuni.fi] [PDF]

2017:

A. Ylä-Outinen, A. Lemmetti, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Kvazaar: HEVC/H.265 4K30p intra encoder,” in Proc. IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2017. [Tuni.fi] [PDF]

J. Räsänen, M. Viitanen, J. Vanne, and T. D. Hämäläinen, “Kvazzup: open software for HEVC video calls,” in Proc. IEEE Int. Symp. Multimedia, Taichung, Taiwan, Dec. 2017. [Tuni.fi] [PDF]

P. Sjövall, V. Viitamäki, A. Oinonen, J. Vanne, T. D. Hämäläinen, and A. Kulmala “Kvazaar 4K HEVC intra encoder on FPGA accelerated airframe server,” in Proc. IEEE Workshop Signal Process. Syst., Lorient, France, Oct. 2017. [Tuni.fi] [PDF]

V. Viitamäki, P. Sjövall, J. Vanne, and T. D. Hämäläinen, “High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA,” in Proc. IEEE Int. Symp. Circuits Syst., Baltimore, Maryland, USA, May 2017. [Tuni.fi] [PDF]

P. Sjövall, V. Viitamäki, J. Vanne, and T. D. Hämäläinen, “High-level synthesis implementation of HEVC 2-D DCT/DST on FPGA,” in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Process., New Orleans, Louisiana, USA, Mar. 2017. [Tuni.fi] [PDF]

2016:

J. Räsänen, M. Viitanen, J. Vanne, T. D. Hämäläinen, M. M. Hannuksela, and V. K. Malamal Vadakital, “RTP/RTCP reception hint tracks for video call recording and playback,” in Proc. IEEE Int. Symp. Multimedia, San Jose, California, USA, Dec. 2016. [Tuni.fi] [PDF]

M. Viitanen, A. Koivula, A. Lemmetti, A. Ylä-Outinen, J. Vanne, and T. D. Hämäläinen, “Kvazaar: open-source HEVC/H.265 encoder,” in Proc. ACM Int. Conf. Multimedia, Amsterdam, The Netherlands, Oct. 2016. [Tuni.fi] [PDF]

M. Viitanen, A. Koivula, J. Vanne, and T. D. Hämäläinen, “Live demonstration: run-time visualization of Kvazaar HEVC intra encoder,” in Proc. IEEE Int. Symp. Circuits Syst., Montreal, Canada, May 2016. [Tuni.fi] [PDF]

2015:

A. Koivula, M. Viitanen, A. Lemmetti, J. Vanne, and T. D. Hämäläinen, “Performance evaluation of Kvazaar HEVC intra encoder on Xeon Phi many-core processor,” in Proc. IEEE Global Conf. Signal Information Process., Orlando, Florida, USA, Dec. 2015. [Tuni.fi] [PDF]

M. Viitanen, A. Koivula, J. Vanne, and T. D. Hämäläinen, “Kvazaar HEVC still image coding on Raspberry Pi 2 for low-cost remote surveillance,” in Proc. IEEE Visual Comm. and Image Proc., Singapore, Dec. 2015. [Tuni.fi] [PDF]

A. Koivula, M. Viitanen, J. Vanne, T. D. Hämäläinen, and L. Fasnacht, “Parallelization of Kvazaar HEVC intra encoder for multi-core processors,” in Proc. IEEE Workshop Signal Process. Syst., Hangzhou, China, Oct. 2015, pp. 1-6. [Tuni.fi] [PDF]

P. Sjövall, J. Virtanen, J. Vanne, and T. D. Hämäläinen, “High-level synthesis design flow for HEVC intra encoder on SoC-FPGA,” in Proc. Euromicro Symp. Digit. Syst. Des., Funchal, Madeira, Portugal, Aug. 2015, pp. 49-56. [Tuni.fi]

M. Viitanen, A. Koivula, A. Lemmetti, J. Vanne, and T. D. Hämäläinen, “Kvazaar HEVC encoder for efficient intra coding,” in Proc. IEEE Int. Symp. Circuits Syst., Lisbon, Portugal, May 2015, pp. 1662-1665. [Tuni.fi] [PDF]

2014:

J. Vanne, M. Viitanen, A. Koivula, and T. D. Hämäläinen, “Comparative study of 8 and 10-bit HEVC encoders,” in Proc. IEEE Visual Comm. and Image Proc., Valletta, Malta, Dec. 2014, pp. 542-545. [Tuni.fi] [PDF]

2012:

M. Viitanen, J. Vanne, T. D. Hämäläinen, M. Gabbouj, and J. Lainema, “Complexity analysis of next-generation HEVC decoder,” in Proc. IEEE Int. Symp. Circuits Syst., Seoul, Korea, May 2012, pp. 882-885. [Tuni.fi] [PDF]


Other papersexpand_more